The present invention relates to a high-speed semiconductor memory device, and more particularly, to an apparatus and method for transmitting and receiving data at a high speed in a read operation and a write operation.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. In order for faster and stable operation of semiconductor memory devices, a variety of circuits inside the semiconductor memory devices must be able to operate at a high speed and transfer signals or data between the circuits at a high speed.
In practice, the operation of the semiconductor memory device is delayed by a control circuit, a data line, and a connecting apparatus, which are used to read data from unit cells or transfer external data to unit cells. In addition, delay occurs when data output from the semiconductor memory device is transferred to devices requiring the data. In a high-speed system, delay occurring in the signal or data transfer may degrade the system performance and lower the operational stability and reliability. Delay occurring in a data transfer path is highly likely to change according to a given operation environment, which will have an adverse effect on the operation of the semiconductor memory device.
Generally, an operational performance of the semiconductor memory device is further improved as a read operation of outputting data from a unit cell after receiving an external command becomes faster. In particular, a time required to output data is a very important performance index in a semiconductor memory device used for processing a large amount of data such as images at a high speed. Furthermore, the system can operate stably when data output from the semiconductor memory device are exactly transferred to a variety of processors.
FIG. 1 is a timing diagram illustrating a read operation of a conventional semiconductor memory device. Specifically, FIG. 1 illustrates an operation of receiving and transmitting data between a semiconductor memory device for graphics and a graphics processing unit (GPU).
Referring to FIG. 1, in a read operation, a typical double data rate (DDR) memory device outputs required data DRAM_DATA in synchronization with rising and falling edges of a memory clock DRAM_CLOCK according to a request of a GPU. In addition, the GPU reads data values input in synchronization with rising and falling edges of the GPU clock GPU_CLK. In this case, the GPU can exactly receive data when the rising and falling edges of the graphic clock GPU_CLK exist in a valid window of data output from the DDR memory device.
In transferring data, a data delay time of t2-t1 occurs due to physical factors between the DDR memory device and the GPU. The DDR memory device outputs data in synchronization with the edges of the clock, but the GPU can exactly receive the data when the edges of the clock are positioned within the valid window, preferably at the center of the valid window. Therefore, a most ideal phase difference between the memory clock DRAM_CLOCK and the graphic clock GPU_CLK is 0.5×UI (where UI represents the valid data window). In this case, a data delay time is about t2−t1+0.5×UI, considering physical factors existing between the DDR memory device and the GPU. Consequently, as illustrated in FIG. 1, the DDR memory device and the GPU operate in synchronization with clocks having different phases. The different clock environment of the DDR memory device and the GPU means that the data being transferred is mismatched with a clock for recognizing the data, that is, a data trigger signal.
In order to solve the mismatch and provide a stable operation, the DDR memory device or the system including the same predefines a delay time occurring between the semiconductor memory device and the GPU. To this end, the DDR memory device or the system uses separate clocks, that is, reference signals, such as a read strobe signal (RDQS) and a write strobe signal (WDQS). Also, an output access time (tAC) and a data strobe signal output access time (tDQSCK) based on the reference clock, or a time (tDQSQ) from the data strobe signal to the data output are specified in the specification of the semiconductor memory device.
Parameters or related information defined in the specification of the semiconductor memory device are physically fixed inside the semiconductor memory device and the GPU. Therefore, it is difficult to ensure a normal data transfer when unexpected operation environment changes occur within a real system. In particular, since the valid data window of a high-speed system becomes narrower, it is not easy to transfer data stably as data increases in a channel between the semiconductor memory device and the GPU.
To solve this problem, the semiconductor memory device and the GPU cope with the high-speed data transfer through data training. The data training refers to a technique that adjusts a skew between data by using a known data pattern between the semiconductor memory device and a controller for stably transferring data for the read and write operations. As one example, a specification describing the performance of a DDR version 3 (DDR3) memory device adopts a write leveling technique for compensating a time difference between a clock (HCLK) and a data strobe signal (DQS) due to delay. Programmable delay components are used in the data strobe signal, so that timing requirements including tDQSS, tDSS and tDSH of the semiconductor memory device can be satisfied by compensating the skew between the strobe signal and the clock through the write leveling.
Recent semiconductor memory devices for graphics have been designed to transfer data at a rate of 4 Gbps. In order to ensure the reliability of the high-speed operation, the data training is specified in the specification of the semiconductor memory devices for graphics.